Supporting Jumps

Learning Outcomes

• Implement a datapath that supports unconditional jumps (jal and jalr).
• Compare the control signals set for jal and jalr.
• Explain why unconditional jumps do not use the branch comparator.

🎥 Lecture Video

🎥 Lecture Video

Datapath updates for jal

To support jal:

• RegFile: We read no registers but write one register rd. The value to write is pc + 4, i.e., the “link” to the next instruction.
• PC: We read from and write to PC. The value to write is pc + imm.

We can reuse many components of our R-, I-, S-, and B-Type datapath. We will need to update two blocks, shown in #fig-jal-new-blocks.

Update the Immediate Generator block and the WBSel mux.

Immediate Generator: Upgrade the Immediate Generator to support immediates in J-Type instructions.

Mux: The WBSel mux must now select between three values for wdata (the data to write to R[rd]):

• Arithmetic and Logical R-Type or I-Type instructions: The output of the ALU (alu), which is now wired both into addr and into the new mux.
• Load instructions: The output of DMEM (mem).
• Jump instructions: pc + 4.

Tracing the jal Datapath

The `jal` datapath. Use the menu bar to trace through the animation or access the [original Google slides](https://docs.google.com/presentation/d/1NTWJNNbw4Pk-2SlUlo8JLNw8fOSHKXvQ/edit?usp=sharing).

1. Instruction Fetch: At the beginning of the clock cycle, read PC and fetch the current instruction from IMEM. Feed pc and pc + 4 to blocks.

   Before the next rising clock edge, set the output of the ALU to the input of PC.

2. Instruction Decode: Build the immediate imm for J-Type instructions. Also configure control logic (see below).

3. Execute: Compute pc + imm using the ALU. Because control signals are ASel=1 and BSel=1, the two muxes before the ALU will select pc and imm, respectively. Because ALUSel=Add, these two values will be added together using the ALU to produce pc + imm.

4. Memory: (We don’t access DMEM, so skip this.)

5. Write Back: Write pc + 4 output to the destination register by connecting the output of the WBSel mux to RegFile’s wdata input.

   Around the next rising clock edge, wdata, RegWEn, and rd should be held stable through setup and hold time of RegFile.

Datapath updates for jalr

To support jalr:

• RegFile: We read one register rs1 and write one register rd. The value to write is pc + 4, i.e., the “link” to the next instruction.
• PC: We read from and write to PC. The value to write is R[rs1] + imm.

We do not need any updates to our datapath to support jalr! Because jalr is I-Type, the immediate generator block already supports it. Instead, for jalr, we need to set our control signals accordingly.

Tracing the jalr Datapath

The `jalr` datapath. Use the menu bar to trace through the animation or access the [original Google slides](https://docs.google.com/presentation/d/1E4qsF1FVE6fhnl1wTnp824rWql7BIc6r/edit?usp=sharing).

1. Instruction Fetch: At the beginning of the clock cycle, read PC and fetch the current instruction from IMEM. Feed pc + 4 to blocks.

   Before the next rising clock edge, set the output of the ALU to the input of PC.

2. Instruction Decode: Fetch R[rs1] from RegFile and build the immediate imm for I-Type instructions. Also configure control logic (see below).

3. Execute: Compute R[rs1] + imm using the ALU. Because control signals are ASel=0 and BSel=1, the two muxes before the ALU will select R[rs1] and imm, respectively. Because ALUSel=Add, the ALU will add these two values together.

4. Memory: (We don’t access DMEM, so skip this.)

5. Write Back: Write pc + 4 output to the destination register and connect the output of the WBSel mux to RegFile’s wdata input.

   Around the next rising clock edge, wdata, RegWEn, and rd should be held stable through setup and hold time of RegFile.

Footnotes

1. Review Control Signals for Stores for an explanation of “don’t care.” ↩ ↩²