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CS61C

RISC-V Arithmetic Instructions II: Bitwise Operations

Learning Outcomes

  • Write assembly to perform bitwise operations.
  • Understand why there are only three RISC-V bitshift operations: sll, srl, and sra (and their immediate equivalents slli, srli, srai).
🎥 Lecture Video

We recommend reviewing the C Bitwise Operations before continuing.

We have previously discussed that in RISC-V, operations determine “type,” i.e., how register contents are treated (see this table). Next, we will see how this concept applies to RISC-V’s instruction set for bitwise operations.

Bitwise Operations

As before, bitwise operations are performed on n-bit operands one bit at a time.

The RV32I ISA provides instructions for common bitwise operations.1. #tab-bitwise shows that most bitwise operations correspond to two instructions:

  • RISC-V: Register. Perform the bitwise operation on two register operands rs1 and rs2, and store the result in a destination register rd.
  • RISC-V: Immediate. Perform the bitwise operation on one register operand rs1 and an immediate imm, and store the result in a destination register rd.

In #tab-rv-bitwise below, hover over each footnote to jump to the corresponding section on this page.

The not pseudoinstruction

In RISC-V, bitwise NOT is a pseudoinstruction and corresponds to a bitwise XOR with the immediate -1:

Notes:

  • A bitwise NOT of the value R[rs1] is defined as a bitwise inversion of all 32 bits of register rs1.
  • Recall from our discussion of XOR properties that for a single bit x, the expression x XOR 1 (x ^ 1) inverts x.
  • The immediate -1 has 32-bit two’s complement signed integer representation 0b 1111 1111 1111 1111 1111 1111 1111 1111.

These three notes together explain #fig-rv32i-not below.

Three aligned 32-bit patterns labeled rs1, minus one, and rd showing how the XOR operation with an all-one immediate flips every bit of rs1, turning a value ending in 0111 into a result ending in 1000 in the destination register rd.

Add immediate instruction in RISC-V and C with negative values.

Show explanation
  • The source register rs1 has value 0b 1111 1111 1111 1111 1111 1111 1111 0111.
  • Destination register rd has value 0b 0000 0000 0000 0000 0000 0000 0000 1000.
  • By definition, this operation is both NOT (a bitwise inversion) and XOR with the 32-bit two’s complement representation of -1.

Shift left

Like all RISC-V arithmetic instructions, the left-shift operation sll must write all 32 bits of the destination register. Recall our discussion of the left shift operation: the expression x << n shifts the bits of x left by n bits, filling the n lower bits with zero. The sll operation therefore fills in these new bits with 0.

Shift right

Recall our discussion of the right shift operation: the expression x >> n shifts the bits of x right by n bits, filling the n lower bits with zero or one. In C, this was determined by x’s type. In RISC-V, the instruction determines what the lower bits are filled in with

  • srl, or Shift Right Logical (srli for immediate). “Zero-extend” and fill the upper bits with 0. This instruction effectively interprets register rs1’s contents as an unsigned integer. Read more in an earlier section.
  • sra, or Shift Right Arithmetic (srai for immediate). Fill in the upper bits with the sign bit of register rs1. This instruction effectively interprets register rs1’s contents as a signedinteger. Read more in an earlier section.

shift arithmetic: signed

Other RISC-V arithmetic instructions

General multiplication is not included in the base RISC-V ISA but is specified as part of common RISC-V extensions. See the mul instruction on the RISC-V green card.

The circuitry for general multiplication is significantly more complicated than the bitwise left- and right-shift operations discussed above. For similar reasons, we do not discuss division, modulo, and floating point operations.5

Practice

Show answer

B. 0x3400.

These instructions are the RISC-V translation of the C practice example when we discussed C bitwise operations. We recommend reviewing that first.

Each line, explained:

  1. Write value 0x000034FF to register x10.

  2. R[x10] << 0x10 is 0x34FF0000. Write this value to register x12.

  3. R[x12] >> 0x8 is 0x0034FF00 because the sign bit of R[x12] is initially 0.

  4. R[x12] & R[x10] is 0x000034FF & 0x0034FF00 is 0x00003400. See #fig-bit-shift from the C practice example.

Footnotes

  1. See the full set of arithmetic instructions on the RISC-V green card. ↩

  2. See the not pseudoinstruction. ↩

  3. See shift left. ↩

  4. See shift right. ↩

  5. We encourage you to read the RISC-V unprivileged ISA for the M Extension and the F extension. ↩