CS61C 计算机体系结构

课程简介

CS 61C: Course Notes

L02 Number Representation

Introduction
Binary, Decimal, Hex
Integer Representations
Signed Representation: Two's Complement
Summary

L03-L08 C

L03 C Basics

Introduction
Compile vs. Interpret
C vs. Java
C Variables
C Syntax
Summary

L04 C Pointers, Arrays, Strings

Introduction
Pointers and Bugs
Arrays
C Strings
Summary

L05 C Memory Management

Introduction
The Stack
The Heap
Implementing Heap Memory
Summary

L06 C Odds and Ends

C Bitwise Operations
Words, Endianness
Linked List: add_front
Linked List: Full Implementation
Summary

L07 C Generics, Function Pointers

Introduction
Generics
Function Pointers
Summary

L08 Floating Point

Motivation: Fixed Point
Normalized Numbers
Normalized Numbers: Practice
Special Numbers
Floating Point: More Discussion
Summary

L09-L12 RISC-V

L09 RISC-V Intro

Introduction
Elements of Architecture: Processor, Registers, and Memory
RISC-V ISA
RISC-V Arithmetic Instructions I: Arithmetic Operations
RISC-V Arithmetic Instructions II: Bitwise Operations
Summary

L10 RISC-V Data Transfer

Load from, Store to
Data Transfer Instructions
Short Examples
Example: Stack Arrays
Summary

L11 RISC-V Decision Making

The Program Counter
Conditional Branches
Loops
Summary

L12 RISC-V Procedures

Procedure Calls
Jumps and Stack Frames
Calling Convention
Recursive Procedure Calls
Summary

L13-L14 RISC-V Instruction Formats

L13 RISC-V Instruction Formats I

Machine Language
R-type Instruction Format
I-Type
S-Type
Summary

L14 RISC-V Instruction Formats II

RISC-V Addressing Modes
B-Type
J-Type
U-Type
Summary

L15 CALL

CALL Overview
Assembler: Object File
Linker: Resolve References
CAL Example: Hello World
Interpretation vs Translation
Summary

L16-L20 Synchronous Digital Systems

L16 Intro to SDS

Synchronous Digital Systems
Transistors and Switches
Summary

L17 Combinational Logic

Logic Gates
Boolean Algebra
Canonical Form, CL Design
Summary

L18 State, Timing

Signals, Waveforms, and the Clock
The Register
Timing a Synchronous System
Finite State Machines
Pipelining for Performance
Summary

L19-L20 Combinational Logic Blocks

Data Multiplexors
Adder/Subtractor
Arithmetic Logic Unit
Summary

L21-L23 Single-Cycle CPU

L21 Single-Cycle CPU Datapath I

Introduction
State Elements on the Datapath
R-Type Datapath, ALU
Supporting Immediates

L22 Single-Cycle CPU Datapath II

Supporting Loads and Stores
Supporting Branches
Supporting Jumps
Supporting U-Type

L23 Single-Cycle CPU Control, Instruction Timing

Control Logic Design
Instruction Timing
Control and Status Registers
Summary

L24-L25 Pipelining

L24 Throughput, Latency, and the 5-Stage Pipeline

Performance Metrics
Pipelining Laundry
The RISC-V 5-Stage Pipeline
Iron Law of Processor Performance
Superscalar
Energy Efficiency
Summary

L25 Hazards

Intro to Hazards
Structural Hazards
Data Hazards
Control Hazards
Summary

L26-L29 Caches

L26 Cache Performance

Library Analogy
Memory Hierarchy, Revisited
Average Memory Access Time (AMAT)
Summary

L27-L28 Cache Design

Cache Terminology
Fully Associative Cache
Direct Mapped Cache
Set-Associative Cache
Summary

L29 Cache Misses and Optimization

Cache Misses
Cache Optimizations
Cache Blocking
Summary

L30-L34 Performance Programming

L30 Amdahl's Law

Amdahl's Law
Loop Unrolling, GCC
DGEMM: Matrix Multiplication
DGEMM: Performance Benchmark
Summary

L31 Flynn's Taxonomy, SIMD

Flynn's Taxonomy
SIMD Architectures
DGEMM: SIMD with Intel Intrinsics
Intel Intrinsics
Summary

L32 MIMD, Thread-Level Parallelism

MIMD Architectures
Threads
OpenMP
DGEMM: MIMD with OpenMP
OpenMP Examples

L33-L34 Synchronization

Data Races, Critical Sections
Cache Coherence
Locks, Atomic Instructions
Summary

L35-L36 Virtual Memory

L35: Intro to Virtual Memory

Virtual Memory and Pages
Address Translation
The \"Memory Manager\"

L36: The TLB, Full Memory Hierarchy

Page Table Design
The Translation Lookaside Buffer
Putting It All Together
Summary

其他

IEC and Base-10 Prefixes
RV32I \"Green Card\"

参考资料

References

JALEE // ASTRO

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CS61C 计算机体系结构

课程简介

CS 61C: Course Notes

L02 Number Representation

Introduction
Binary, Decimal, Hex
Integer Representations
Signed Representation: Two's Complement
Summary

L03-L08 C

L03 C Basics

Introduction
Compile vs. Interpret
C vs. Java
C Variables
C Syntax
Summary

L04 C Pointers, Arrays, Strings

Introduction
Pointers and Bugs
Arrays
C Strings
Summary

L05 C Memory Management

Introduction
The Stack
The Heap
Implementing Heap Memory
Summary

L06 C Odds and Ends

C Bitwise Operations
Words, Endianness
Linked List: add_front
Linked List: Full Implementation
Summary

L07 C Generics, Function Pointers

Introduction
Generics
Function Pointers
Summary

L08 Floating Point

Motivation: Fixed Point
Normalized Numbers
Normalized Numbers: Practice
Special Numbers
Floating Point: More Discussion
Summary

L09-L12 RISC-V

L09 RISC-V Intro

Introduction
Elements of Architecture: Processor, Registers, and Memory
RISC-V ISA
RISC-V Arithmetic Instructions I: Arithmetic Operations
RISC-V Arithmetic Instructions II: Bitwise Operations
Summary

L10 RISC-V Data Transfer

Load from, Store to
Data Transfer Instructions
Short Examples
Example: Stack Arrays
Summary

L11 RISC-V Decision Making

The Program Counter
Conditional Branches
Loops
Summary

L12 RISC-V Procedures

Procedure Calls
Jumps and Stack Frames
Calling Convention
Recursive Procedure Calls
Summary

L13-L14 RISC-V Instruction Formats

L13 RISC-V Instruction Formats I

Machine Language
R-type Instruction Format
I-Type
S-Type
Summary

L14 RISC-V Instruction Formats II

RISC-V Addressing Modes
B-Type
J-Type
U-Type
Summary

L15 CALL

CALL Overview
Assembler: Object File
Linker: Resolve References
CAL Example: Hello World
Interpretation vs Translation
Summary

L16-L20 Synchronous Digital Systems

L16 Intro to SDS

Synchronous Digital Systems
Transistors and Switches
Summary

L17 Combinational Logic

Logic Gates
Boolean Algebra
Canonical Form, CL Design
Summary

L18 State, Timing

Signals, Waveforms, and the Clock
The Register
Timing a Synchronous System
Finite State Machines
Pipelining for Performance
Summary

L19-L20 Combinational Logic Blocks

Data Multiplexors
Adder/Subtractor
Arithmetic Logic Unit
Summary

L21-L23 Single-Cycle CPU

L21 Single-Cycle CPU Datapath I

Introduction
State Elements on the Datapath
R-Type Datapath, ALU
Supporting Immediates

L22 Single-Cycle CPU Datapath II

Supporting Loads and Stores
Supporting Branches
Supporting Jumps
Supporting U-Type

L23 Single-Cycle CPU Control, Instruction Timing

Control Logic Design
Instruction Timing
Control and Status Registers
Summary

L24-L25 Pipelining

L24 Throughput, Latency, and the 5-Stage Pipeline

Performance Metrics
Pipelining Laundry
The RISC-V 5-Stage Pipeline
Iron Law of Processor Performance
Superscalar
Energy Efficiency
Summary

L25 Hazards

Intro to Hazards
Structural Hazards
Data Hazards
Control Hazards
Summary

L26-L29 Caches

L26 Cache Performance

Library Analogy
Memory Hierarchy, Revisited
Average Memory Access Time (AMAT)
Summary

L27-L28 Cache Design

Cache Terminology
Fully Associative Cache
Direct Mapped Cache
Set-Associative Cache
Summary

L29 Cache Misses and Optimization

Cache Misses
Cache Optimizations
Cache Blocking
Summary

L30-L34 Performance Programming

L30 Amdahl's Law

Amdahl's Law
Loop Unrolling, GCC
DGEMM: Matrix Multiplication
DGEMM: Performance Benchmark
Summary

L31 Flynn's Taxonomy, SIMD

Flynn's Taxonomy
SIMD Architectures
DGEMM: SIMD with Intel Intrinsics
Intel Intrinsics
Summary

L32 MIMD, Thread-Level Parallelism

MIMD Architectures
Threads
OpenMP
DGEMM: MIMD with OpenMP
OpenMP Examples

L33-L34 Synchronization

Data Races, Critical Sections
Cache Coherence
Locks, Atomic Instructions
Summary

L35-L36 Virtual Memory

L35: Intro to Virtual Memory

Virtual Memory and Pages
Address Translation
The \"Memory Manager\"

L36: The TLB, Full Memory Hierarchy

Page Table Design
The Translation Lookaside Buffer
Putting It All Together
Summary

其他

IEC and Base-10 Prefixes
RV32I \"Green Card\"

参考资料

References

CS61C

Summary

And in Conclusion $\dots$

Textbook Readings

P&H 1.7, 1.8, 2.11, 4.10, 4.11, 5.10, 6.1-6.3, 6.5, 6.7

Additional References

Exercises

Check your knowledge!

Conceptual Review

Exercise

True/False? Using write-through caches removes the need for cache coherence.

Solution

False. You have a copy. I do a write (through, to memory). How do you get updated when you do a read?

Exercise

True/False? Every processor store instruction must check contents of other caches.

Solution

False. That’s the point of these protocols, to know if others have copies and whether I need to just do a store or do other work.

Exercise

True/False? Only one processor can cache any memory location at one time.

Solution

False. What if they’re all doing reads? That would be inefficient.

Short Exercises

← Locks, Atomic Instructions Virtual Memory and Pages →

CONTENTS

And in Conclusion…\dots…
Textbook Readings
Additional References
Exercises
Conceptual Review
Short Exercises

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