Summary

And in Conclusion$\dots$

🎥 Lecture Video

🎥 Lecture Video

Our single-cycle datapath is a synchronous digital system that has the capabilities of executing RISC-V instructions in one cycle each. It is divided into multiple stages of execution, where each stage is responsible for a completing a certain task.

1. IF Instruction Fetch:
   • Send address to the instruction memory (IMEM), and read IMEM at that address.
   • Hardware units: PC register, +4 adder, PCSel mux, IMEM
2. ID Instruction Decode:
   • Generate control signals from the instruction bits, generate the immediate, and read registers from the RegFile.
   • Hardware units: RegFile, ImmGen
3. EX Execute:
   • Perform ALU operations, and do branch comparison.
   • Hardware units: ASel mux, BSel mux, branch comparator, ALU
4. MEM Memory
   • Read from or write to the data memory (DMEM).
   • Hardware units: DMEM
5. WB Writeback
   • Write back either PC + 4, the result of the ALU operation, or data from memory to the RegFile.
   • Hardware units: WBSel mux, RegFile

The critical path changes based on instruction. Not all instructions use all hardware units, and therefore not all instructions are active in all five phases of execution (“stages” is the terminology we use for pipelined processors).

The controller (e.g., control logic subcircuit) specifies how to execute instructions and it is implemented as ROM (read-only-memory) or as logic gates.

Textbook Readings

P&H 4.1, 4.3, 4.4, 4.5

Exercises

Solution

True Since every instruction must read from IMEM during the instruction fetch stage, making the IMEM faster will speed up every single instruction.

Solution

False You may only use either the immediate generator or the value in register rs2. Notice in our datapath, there is a mux with a signal (BSel) that decides whether we use the output of the immediate generator or the value in rs2.

Solution

False All units are active in each cycle, but their output may be ignored (gated) by control signals.

Solution

False Each stage depends on the value produced by the stage before it (e.g., instruction decode depends on the instruction fetched).

Solution

True For all other instructions, we don’t need to read the data that is read out from DMEM, and thus don’t need to wait for the output of the MEM stage.