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CS61C

U-Type

Learning Outcomes

  • Explain why U-Type is needed for building wide immediates.
  • Translate the pseudoinstruction li (Load Immediate) into machine code.
🎥 Lecture Video

Recall that I-Type arithmetic instructions encode an sign extension 12-bit immediate as a two’s complement integer, which is then sign-extended to a 32-bit value. While constants are frequently short and fit into the 12-bit I-Type fields, we inevitably need to encode wide immediates to build numberic constants larger than the I-type’s 12-bit imm.

RISC-V achieves wide immediates as follows:

  • Specify 32-bit constants using two instructions: an I-Type arithmetic instruction for the 12-bit lower immediate, i.e., bits 0 to 11; and and a different instruction for the 20-bit upper immediate, i.e., bits 12 to 31. (Again, reduced instruction set!)
  • Define an instruction format, U-Type (the “U” is for Upper immediate), that can be used for instructions that specify upper immediates.

There are two U-Type instructions: lui and auipc. These are located in the “Other” section of the RISC-V green card.

Load Upper Immediate (lui)

From the P&H textbook (Chapter 2.10), one such instruction, lui, is Load Upper Immediate:

…load a 20-bit constant into bits 12 through 31 of a register. The rightmost 12 bits are filled with zeros.

In #tab-lui, we call this upper immediate immu and the 32-bit immediate imm.

As shown in #fig-u-type-immu, imm = immu << 12; this 32-bit numeric constant imm is then written to register rd.

32-bit U-Type instruction format: the 20-bit field immu sits in bits 31–12, bits 11–0 are zero, and the full immediate imm is formed by concatenating immu with twelve zero in the least significant bit positions.

For U-Type instructions, immu is the top 20 bits of a 32-bit-wide numeric constant imm imm.

Load Immediate Pseudoinstruction

With this new instruction, we can now return to translating the li pseudoinstruction, Load Immediate. When we introduced load immediate, you may have noticed a footnote in #tab-mv-li:

This description is incomplete given the range of imm in addi. See the green-card and a later section for the full translation of load immediates.

In other words, when li must use a numeric constant wider than the 12 bits accommodated by the I-Type addi’s imm field it translates to two instructions: lui and addi.

PseudoinstructionNameDescriptionTranslation
li rd immLoad ImmediateR[rd] = immlui (if needed), addi

In other words, li translates to addi when the immediate is between -2048 and 2047. For anything larger, li translates to two instructions: lui and addi.

In general, the compiler or assembler will break large constants across the lui and addi instructions, as needed. After all, there are some important caveats to this process. Hover over the two footnotes below before continuing.

  • lui to set the upper 20 bits1
  • addi to “set” the lower 12 bits2
Show Explanation
  1. lui sets x10 to 0x87654000. Note 0x87654 is 20 bits.
  2. addi sets x10 to 0x87654321 = 0x87654000 + 0x00000321, where the latter operand is the sign-extended version of the 12-bit immediate 0x321.
Show Explanation

Let’s first consider the strawman3, which does not work:

lui  x10 0xB0BAC
addi x10 x10 0xAFE

Remember, the addi instruction sign-extends the 12-bit immediate imm. If the sign bit of imm is set, then imm is negative, subtracting 1 from the upper 20 bits set by the previous lui instruction.

  1. lui sets x10 to 0xB0BAC000.
  2. addi sets x10 to 0xB0BAC000 + 0xFFFFAFE, because the 12-bit immediate 0xAFE is a two’s complement negative number. x10 is then set to 0xB0BABAFE.

#fig-li-lui-strawman “cutely”4 illustrates this “subtraction by one” using hexadecimal arithmetic and algebraic properties.

Arithmetic example showing the addition of hexadecimal value 0xB0BAC000 with 0xFFFFFAFE to produce the resulting 0xB0BABAFE word. The arithmetic is separated into an addition of the least significant three nibbles with three 0s, and the most significant 5 nibbles added to -1, represented with five hexadecimal Fs.

When addi’s immediate imm is signed, a naive lui immediate immu will yield an incorrect numeric constant.

To solve this, know that addi will always follow lui when resolving a li pseudoinstruction, and addi will always sign-extend its immediate imm. So if addi’s 12-bit imm field is negative, proactively add 1 to lui’s 20-bit immu field:

lui  x10 0xB0BAD
addi x10 x10 0xAFE
  1. lui sets x10 to 0xB0BAD000.
  2. addi sets x10 to 0xB0BAD000 + 0xFFFFAFE, because the 12-bit immediate 0xAFE is a two’s complement negative number. x10 is then set to 0xB0BACAFE.

Add Upper Immediate to PC

Coming soon. Used for J-Type instructions.

U-Type: Fields

In order to translate lui and auipc to machine code, we need an instruction format that supports 20-bit immediates. The U-Type instruction format is only used by lui and auipc and is the one of the last rows of the instruction format table of the RISC-V green card.

U-type instruction format layout with syntax opname rd immu and fields imm[31:12] (bits 31–12), rd (bits 11–7), and opcode (bits 6–0); additional notes specify that immu is the upper 20 bits of a 32-bit immediate produced by shifting that field left by 12.

The U-Type Instruction Format.

U-Type has only three fields (@fig-u-type):

  • Register operand: The U-Type field rd is the destination register to put the immediate.

  • Opcode: The U-Type field opcode specifies the operation: auipc or lui (@tab-u-type).

  • Constant operand: The upper immediate field (we’ll call it immu) specifies a 20-bit immediate value. immu is left-shifted by 12 to form the upper 20 bits of a 32-bit numeric constant imm (@fig-u-type-immu).

Footnotes

  1. And zero out lower 12 bits ↩

  2. “Set” as in, add a sign-extended 12-bit immediate ↩

  3. Wikipedia: Straw Man ↩

  4. For some definition of “cute”; here, “cool math” ↩